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document number: mc33395 rev 4.0, 2/2007 freescale semiconductor technical data * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, inc., 2007. all rights reserved. three-phase gate driver ic the 33395 simplifies the design of high-power bldc motor control design by combining the gate drive, charge pump, current sense, and protection circuitry necessary to drive a three-phase bridge configuration of six n-channel power mosfets. mode logic is incorporated to route a pulse width modulation (pwm) or a complementary pwm output signal to either low-side or high-side mosfets of the bridge. detection and drive circuitry are also incorporated to control a reverse battery protection high-side mosfet switch. pwm frequencies up to 28 khz are possible. built-in protection circuitry prevents damage to the mosfet bridge as well as the drive ic and includes overvoltage shutdown , overtemperature shutdown, overcurrent shutdown, and undervoltage shutdown. the device is parametrically spec ified over ambient temperature range of -40 c t a 125 c and 5.5 v v ign 24 v supply. features ? drives six n-channel low r ds(on) power mosfets ? built-in charge pump circuitry ? built-in current sense compar ator and output drive current limiting ? built-in pwm mode control logic ? built-in circuit protection ? designed for fractional to integral hp bldc motors ? 32-pin soic wide body surface mount package ? 33395 incorporates a <5.0 s shoot-through suppression timer ? 33395t incorporates a <1.0 s shoot-through suppression timer ? pb-free packaging designated by suffix code ew figure 1. 33395 simplified application diagram three-phase gate driver ic dwb suffix ew suffix (pb-free) 98arh99137a 32-pin soicw 33395 33395t ordering information device temperature range (t a ) package mc33395dwb/r2 - 40c to 125c 32 soicw mc33395ew/r2 32 soicw (pb-free) mcz33395ew/r2 mc33395tdwb/r2 32 soicw mc33395tew/r2 32 soicw (pb-free) 3 3 2 v dd v pwr mcu v dd h h h n s s n vgdh vign vdd cp1l cp2h cp2l cp1h cres hse1?3 mode0?1 pwm agnd lse1?3 pgnd vignp gdh1 gdh2 gdh3 src1 src2 src3 gdl1 gdl2 gdl3 -isens +isens 33395
analog integrated circuit device data 2 freescale semiconductor 33395 internal block diagram internal block diagram figure 2. 33395 simplifi ed internal block diagram low voltage reset overvoltage shutdown osc. charge pump drive limiting gate drive circuits control logic shutdown + - lh cp1h cp1l cp2h cp2l cpres vgdh gdh1 gdh2 gdh3 src1 src2 src3 gdl1 gdl2 gdl3 vignp vign vdd +isens -isens mode0 mode1 pwm hse1 hse2 hse3 lse1 lse2 lse3 agnd pgnd low overvoltage osc. charge drive limiting gate control overtemperature + - lh logic drive circuits pump shutdown voltage reset shutdown test
analog integrated circuit device data freescale semiconductor 3 33395 pin connections pin connections figure 3. 33395 pin connections table 1. 33395 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 9 . pin number pin name pin function formal name definition 1 cp2h charge pump cap high potential pin connection for secondary charge pump capacitor 2 cpres input charge pump reserve cap input from external reservoir capacitor for charge pump 3 vign input input voltage input from ignition level supp ly voltage for power functions 4 vgdh output high-side gate voltage output full-time gate drive for auxiliary high-side power mosfet switch 5 vignp input input voltage protected input from protected ignition le vel supply for power functions 6 src1 sensor high-side sense sense for high-side source voltage, phase 1 7 gdh1 output gate drive high output for gate high-side, phase 1 8 gdl1 output output for gate output for gate drive low-side, phase 1 9 src2 sensor high-side sense sense for high-side source voltage, phase 2 10 gdh2 output gate drive high output for gate high-side, phase 2 11 gdl2 output output for gate output for gate drive low-side, phase 2 12 src3 sensor high-side sense sense for high-side source voltage, phase 3 13 gdh3 output gate drive high output for gate drive high-side, phase 3 14 gdl3 output gate drive low output for gate drive low-side, phase 3 15 pgnd ground power ground ground pins for power functions 16 test n/a test pin this should be connected to ground or left open 17 -isens input is minus inverting input for current limit comparator 18 +isens input is plus non-inverting input for current limit comparator 19 agnd ground analog ground ground pin for logic functions 20 vdd power logic supply voltage supply voltage for logic functions 21 pwm input pulse width modulator input for pulse width modulated driver duty cycle cp2l 1 lse2 lse3 hse1 hse2 hse3 mode0 mode1 pwm vdd +isens -isens agnd lse1 cp1h cp1l cp2h vignp src1 gdh1 gdl1 src2 gdh2 gdl2 src3 gdh3 pgnd test gdl3 vgdh cpres vign 8 9 10 11 12 13 14 15 16 3 4 5 6 7 2 32 25 24 23 22 21 20 19 18 17 30 29 28 27 26 31
analog integrated circuit device data 4 freescale semiconductor 33395 pin connections 22 mode1 input mode control bit 1 input for mode control selection 23 mode0 input mode control bit 0 input for mode control selection 24 hse3 input high-side enable input for high-side enable logic, phase 3 25 hse2 input high-side enable input for high-side enable logic, phase 2 26 hse1 input high-side enable input for high-side enable logic, phase 1 27 lse3 input low-side enable input for low-side enable logic, phase 3 28 lse2 input low-side enable input for low-side enable logic, phase 2 29 lse1 input low-side enable input for low-side enable logic, phase 1 30 cp1l input external pump capacitor input from external pump capacitor for charge pump and secondary pins 31 cp1h input external pump capacitor input from external pump capacitor for charge pump and secondary pins 32 cp2l input charge pump capacitor input from external reservoir, external pump capacitors for charge pump, and secondary pins table 1. 33395 pin de finitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 9 . pin number pin name pin function formal name definition
analog integrated circuit device data freescale semiconductor 5 33395 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise noted. rating symbol value unit vign supply voltage v ign -15.5 to 40 vdc vignp load dump survival v ignp ld -0.3 to 65 vdc vdd logic supply voltage (fail safe) v dd -0.3 to 7.0 vdc logic input voltage (lsen, hsen, pwm, and moden) v in 0.3 to 7.0 vdc start up current v ignp i vignstartup 100 ma esd voltage (1) human body model machine model v esd1 v esd2 500 200 v storage temperature t stg -65 to 160 c operating ambient temperature t a -40 to 125 c operating case temperature t c -40 to 125 c maximum junction temperature t j 150 c power dissipation (t a = 25c) p d 1.5 w peak package reflow temperature during reflow (2) , (3) t pprt note 3 c thermal resistance, junction-to-ambient r ja 65 c/ w notes 1. esd1 testing is performed in accor dance with the human body model (c zap = 100 pf, r zap = 1500 ? ), esd2 testing is performed in accordance with the machine model (c zap = 200 pf, r zap = 0 ? ). 2. pin soldering temperature limit is for 10 seconds maximum dur ation. not designed for immersion soldering. exceeding these lim its may cause malfunction or permanent damage to the device. 3. freescale?s package reflow capability m eets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.freescale.com, search by part number [e.g. remove pref ixes/suffixes and enter the core id to view all orderable parts . (i.e. mc33xxxd enter 33xxx), and review parametrics.
analog integrated circuit device data 6 freescale semiconductor 33395 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electric al characteristics characteristics noted under conditions -40 c t a 125 c, 5.5 v v ignp 24 v unless otherwise noted. typical values reflect approximate parameter mean at t a = 25 c under normal conditions unless otherwise noted. characteristic symbol min typ max unit power input v ign current @ 5.5 v ? 24 v, v dd = 5.5 v i ign ? 0.2 1.0 ma v ignp current @ 5.5 v ? 24 v, v dd = 5.5 v i ignp ? ? 100 ma v ignp overvoltage shutdown v ignp sd 25 33 36.5 v v ignp voltage v ignp 5.5 ? 24 v v dd current @ 5.5 vdc, 5.5 v v ignp 24 v i v dd ? 1.8 4.0 ma v dd low-voltage reset level v dd(reset) 2.5 3.2 4.0 v v dd one-time fuse (logic supply) ? 7.0 ? ? v input / output input current at v dd = 5.5 v lsen, hsen, pwm, and moden = 3.0 v i in 5.0 12 25 a input threshold at v dd = 5.5 v lsen, hsen, pwm, and moden (4) v th 1.0 2.0 3.0 v v scrn source sense voltage src1, src2, src3 v scrn -0.3 v ignp 24 v comparator input offset voltage v inp(offset) 5.0 14 20 mv comparator input bias current v inp(bias) -500 -170 500 na comparator input offset current i inp(offset) -300 -3.0 300 na common mode voltage (5) v cmr 0 ? v dd - 2.0 v dc comparator differential input voltage (5) v inpdiff -v dd ? +v dd v charge pump voltage v ign (6) v ignp = 5.5 v, i c res = 1.0 ma v ignp = 9.0 v, i c res = 1.0 ma v ignp = 12 v, i c res = 5.0 ma v ignp = 24 v, i c res = 1.0 ma v ignp = 24 v, i c res = 5.0 ma v cres - v ignp 4.0 4.0 4.5 8.0 4.5 6.0 7.5 10 16 12 18 18 18 18 18 v v gdh output voltage with gdhn in on state v ignp = 5.5 v, i gdhn = 1.0 ma v ignp = 12 v, i gdhn = 5.0 ma v ignp = 24 v, i gdhn = 5.0 ma v gdhn( on ) - v srcn 4.0 4.0 4.5 5.2 9.0 11 18 18 18 v v gdh output voltage with gdhn in off state v ignp = srcn = 14 v, i gdhn = 1.0 ma v gdhn( off ) -1.0 0.6 1.0 v notes 4. logic inputs lsen, hsen, pwm, and moden have internal 20 a internal sinks. 5. guaranteed by design and charac terization. not production tested. 6. the charge pump has a positive temperature coefficient. therefor e the min?s occur at -40c, typ?s at 25c, and max?s at 125c .
analog integrated circuit device data freescale semiconductor 7 33395 electrical characteristics static electrical characteristics input / output (continued) v gdl low-side output voltage gdhn in on state v ignp = 5.5 v, i gdln = 1.0 ma v ignp = 12 v, i gdln = 5.0 ma v ignp = 24 v, i gdln = 0.0 ma v ignp = 24 v, i gdln = 5.0 ma v gdl( on ) 5.0 8.0 8.0 8.0 8.0 14 17 16 18 18 19 19 v v gdl output voltage gdhn in off state v ignp = 14 v, i gdln = 1.0 ma v gdl(off) -1.0 0.3 1.0 v thermal shutdown (7) t lim 160 ? 190 c notes 7. guaranteed by design and charac terization. not production tested. table 3. static electrical characteristics (continued) characteristics noted under conditions -40 c t a 125 c, 5.5 v v ignp 24 v unless otherwise noted. typical values reflect approximate parameter mean at t a = 25 c under normal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 8 freescale semiconductor 33395 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics timing diagram figure 4. shoot-through suppression table 4. dynamic electri cal characteristics characteristics noted under conditions -40 c t a 125 c, 5.5 v v ignp 24 v unless otherwise noted. typical values reflect approximate parameter mean at t a = 25 c under normal conditions unless otherwise noted. characteristic symbol min typ max unit high-side (gdhn) and low-side drivers (gdhn) rise time (25% to 75%), c iss value = 2000 pf (8) t rh ? 0.35 1.5 s high-side (gdhn) and low-side drivers (gdhn) fall time (75% to 25%), c iss value = 2000 pf (8) t fh ? 0.25 1.5 s shoot-through suppression time delay (33395) (8) , (9) 33395 33395t t d1, t d2 1.0 0.2 3.0 0.65 5.5 1.0 s current limit time delay (10) t ilimdelay 1.5 2.8 5.0 s notes 8. see figure 4 , page 8 . 9. shoot-through suppression time delay is provided to prevent directly connected high- and lo w-side mosfets from being on simultaneously. 10. current limit time delay: the internal comparator places th e device in the current limit mode when the comparator output goe s low and sets an internal logic bit. this ta kes a finite amount of time and is stated as the current limit time delay. 100 75 25 0 100 75 25 0 t rh t fh t fl t rl time gdln, gate v (%) gdhn srcn (%) t d2 t d1
analog integrated circuit device data freescale semiconductor 9 33395 functional description introduction functional description introduction the 33395 and 33395t devices are designed to provide the necessary drive and control signal buffering and amplification to enable a dsp or mcu to control a three- phase array of power mosfets such as would be required to energize the windings of powerful brushless dc (bldc) motors. it contains built-in charge pump circuitry so that the mosfet array may consist entirely of n-channel mosfets. it also contains feedback sensing circuitry and control circuitry to provide a robust overall motor control design. functional pin description charge pump capacitor (cp2h) high potential pin connection for secondary charge pump capacitor charge pump reserve capacitor (cpres) input from external reservoir capacitor for charge pump input voltage (vign) input from ignition level supply voltage for power functions high-side gate voltage (vgdh) output full-time gate drive for auxiliary high-side power mosfet switch input voltage protected (vignp) input from protected igniti on level supply for power functions high-side sense (src1, src2, src3) sense for high-side source voltage, phase 1/2/3 gate drive high (gdh1, gdh2, gdh3) output for gate high-side, phase 1/2/3 output for gate (gdl1, gdl2, gdl3) output for gate drive low-side, phase 1 power ground (pgnd) ground pins for power functions test pin (test) this should be connected to ground or left open is minus (-isens) inverting input for cu rrent limit comparator is plus (+isens) non-inverting input for current limit comparator analog ground (agnd) ground pin for logic functions logic supply voltage (vdd) supply voltage for logic functions pulse width modulator (pwm) input for pulse width modulated driver duty cycle mode control bit 1 (mode1) input for mode control selection mode control bit 0 (mode0) input for mode control selection high-side enable (hse3, hse2, hse1) input for high-side enable logic, phase 1/2/3 low-side enable (lse3, lse2, lse1) input for low-side enable logic, phase 1/2/3 external pump capacitor (cp1l, cp1h) input from external pump capacitor for charge pump and secondary pins charge pump capacitor (cp2l) input from external reservoir, external pump capacitors for charge pump, and secondary pins
analog integrated circuit device data 10 freescale semiconductor 33395 functional description functional internal block description functional internal block description gate drive circuits the gate drive outputs (gdh 1, gdh2, etc.) supply the peak currents required to turn on and hold on the mosfets, as well as turn off and hold off the mosfets. charge pump the current capability of the char ge pump is sufficient to supply the gate drive circuit? s demands when pwming at up to 28 khz. two external charge pump capacitors and a reservoir capacitor are required to complete the charge pump?s circuitry. charge reservoir capacitance is a function of the total mosfet gate charge (q g ) gate drive voltage level relative to the source (v gs ) and the allowable sag of the drive level during the turn-on interval (v sag ). c res can be expressed by the following formula: for example, for q g = 60 nc, v gs = 14 v, v sag = 0.2 v: proper charge pump capacitance is required to maintain, and provide for, adequate gat e drive during high demand turn-on intervals. use the following formula to determine values for c p1 and c p2 : for example, for the above determination of c res = 0.15 f: by averaging these two values, the proper c p n value can be determined: c p1 and c p2 =(0.0075 f + 0.015 f) 2 = 0.01 f thermal shutdown function the device has internal temperature sensing circuitry which activates a protective sh utdown function should the die reach excessively elevated temperatures. this function effectively limits power dissipation and thus protects the device. overvoltage shut down function when the supply voltage (v ign ) exceeds the specified over- voltage shutdown level, t he part will automatically shut down to protect both internal circuits as well as the load. operation will resume upon return of v ign to normal operating levels. low voltage r eset function when the logic supply voltage (v dd ) drops below the minimum voltage level or when the part is initially powered up, this function will turn off and hold off the external mosfets until the voltage increases above the minimum voltage level required for normal operation. control logic the control logic block controls when the low-side and high-side drivers are enabled. th e logic implements the truth table found in the specificat ion and monitors the m0, m1, pwm, cl, ot, ov, lse, and hse pins. note that the drivers are enabled 3 s after the pwm edge. during complimentary chop mode the high-side and low-side drives are alternatively enabled and disabled during the pwm cycle. to prevent shoot-through current, the high-side drive turn-on is delayed by t d1 , and the low-side drive turn on is delayed by t d2 (see figure 4 , page 8 ). note that the drivers are disabled during an overtemperature or overvoltage fault. a flip-flop keeps the drive off until the following pwm cycle. this prevents erratic operation during fault conditions. the current limit circuit also uses a flip-flop for latching the drive off until the following pwm cycle. note pwm must be toggled afte r por, thermal limit, or overvoltage faults to re-enable the gate drivers. vgdh the vgdh pin is used to provide a gate drive signal to a reverse battery protection mosfet. if reverse battery protection is desired, v ign would be applied to the source of an external mosfet, and the drain of the mosfet would then deliver a "protected" supply voltage (v ignp ) to the three phase array of external mosfets as well as the supply voltage to the v ignp pin of the ic. in a reverse polarity event (e.g., an erroneous installation of the system battery), the v gdh signal will not be supplied to the external protection mo sfet, and the mosfet will remain off and thus prevent reverse polarity from being applied to the load and the vi gnp supply pin of the ic. high-side gate drive circuits outputs gdh1, gdh2, and gdh3 provide the elevated drive voltage to the high-side external mosfets (hs1, hs2, and hs3; see figure 5 , page 13 ). these gate drive outputs supply the peak currents required to turn on and hold on the high-side mosfets, as well as turn off the mosfets. these gate drive circuits are powered from an internal charge pump, and therefore compensat e for voltage dropped across the load that is reflected to the source-gate circuits of the high-side mosfets. low-side gate drive circuits outputs gdl1, gdl2, and gdl3 provide the drive voltage to the low-side external mosfets (ls1, ls2, and ls3; see c res = q g x v gs 2 x v gs x v sag - v sag 2 c res = (60 nc) x (14 v) 2 x (14 v) x (0.2 v) - (0.2) 2 = 0.15 f c res 20 < c p1 = c p2 < 10 c res 0.15 f 20 = 0.075 f, lower limit; and 10 0.15 f = .015 f, upper li m
analog integrated circuit device data freescale semiconductor 11 33395 functional description functional internal block description figure 5 ). these gate drive output s supply the peak currents required to turn on and hold on the low-side mosfets, as well as turn off the mosfets. v dd fuse the v dd supply of the 33395 ic has an internal fuse, which will blow and set all outputs of the device to off, if the v dd voltage exceeds that stated in the maximum rating section of the data sheet. when this fuse blows, the device is permanently disabled. i sens inputs the +i sens and -i sens pins are inputs to the internal current sense comparator. in a typical application, these would receive a a low-pass filtered voltage derived from a current sense resistor placed in series with the ground return of the three-phase output bridge. when triggered by the comparator, the cl (current limit) bit of the internal error register is set, and the output gate drive pairs (i.e., gdh1 and gdl1, gdh2 and gdl2, gdh3 and gdl3), are controlled such that current will cease flowing through the load (refer to table 5 , truth table, page 12 ). overtemperature and overvoltage shutdown circuits internal monitoring is provid ed for both over temperature conditions and over voltage c onditions. when any of these conditions presents itself to the ic, the corresponding internally set bits of the error register are set, and the output gate drive pairs (i.e., gdh1 and gdl1, gdh2 and gdl2, gdh3 and gdl3), are controlled such that current will cease flowing through the load (refer to table 5 ). lse and hse input circuits the low-side enable input pins (lse1, lse2, lse3) and high-side enable input pins (hse1, hse2, hse3) form the input pairs (hse1 and lse1, hse2 and lse2, hse3 and lse3) which set the logic states of the output gate drive pairs (i.e., gdh1 and gdl1, gdh2 and gdl2, gdh3 and gdl3) in accordance with the logic set forth in the truth table ( page 12 ). typically these inputs are supplied from an mcu or dsp to provide the phasing of the currents applied to a brushless dc motor's stator coils via the output mosfet pairs. pwm input the pulse width modulation input provides a single input pin to accomplish pwm modulation of the output pairs in accordance with the states of the mode 0 and mode 1 inputs as set forth in the truth table ( page 12 ). mode selection inputs the mode selection inputs (mode 0 and mode 1) determine the pwm implementat ion of the output pairs in accordance with the logic set forth in the truth table ( page 12 ). pwming can thus be set to occur either on the high-side mosfets or the low-side mosfets, or can be set to occur on both the high-side and low-side mosfets as "complementary chopping". test pin this pin should be grounded or left floating (i.e., do not connect it to the printed circuit board). it is used by the automated test equipment to verify proper operation of the internal overtemperature shut down circuitry. this pin is susceptible to latch-up and therefore may cause erroneous operation or device failure if co nnected to external circuitry.
analog integrated circuit device data 12 freescale semiconductor 33395 functional device operation operational modes functional device operation operational modes table 5. truth table the logic state of each output pair, gdln and gdhn (n = 1, 2, 3), is a function of its corre sponding input pair, lsen and hsen (n = 1, 2, 3), along with the logic states of the moden and pwm inputs and the inter nally set overtemperature shutdown (ot), overvoltage (ov), and current limit (cl) bits provided in this table. normal operation switching modes internally set bits input pairs (e.g., lse2 and hse2) output pairs (e.g., gdl2 and gdh2) mode1 mode0 ot ov cl lsen hsen gdln gdhn 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 pwm 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 1 0 pwm pwm 0 1 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 pwm 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 1 pwm pwm 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 1 0 0 fault mode operation switching modes internally set bits input pairs (e.g., lse2 and hse2) output pairs (e.g., gdl2 and gdh2) mode1 mode0 ot ov cl lsen hsen gdln gdhn 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 1 0 1 0 1 0 0 0 1 1 1 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 1 0 1 1 0 1 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0 0 x x x 1 x x x 0 0 x x 1 x x x x 0 0
analog integrated circuit device data freescale semiconductor 13 33395 typical applications operational modes typical applications figure 5. typical application diagram lse3 lse2 lse1 cp1l cp1h cp2l hse2 hse1 agnd vdd pwm mode1 mode0 hse3 -isens +isens src1 vignp vgdh vign cpres cp2h gdl1 gdh1 gdl3 gdh3 src3 gdl2 gdh2 src2 test pgnd 6 5 4 3 2 1 8 7 14 13 12 11 10 9 16 15 27 28 29 30 31 32 25 26 19 20 21 22 23 24 17 18 mcu + - to motor ls3 ls2 ls1 hs1 hs2 hs3 r sense 5.0 v 12 v + +
analog integrated circuit device data 14 freescale semiconductor 33395 packaging package dimensions packaging package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the 98arh99137a listed below. dwb suffix ew suffix (pb-free) 32-pin plastic package 98arh99137a issue a notes: 1. all dimensions are in millimeters. 2. dimensioning and tolerancing per asme y14.5m, 1994. 3. datums b and c to be determined at the plane where the bottom of the leads exit the plastic body. 4. this dimension does not include mold flash, protrusion or gate burrs. mold flash, protrusion or gate burrs shall not exceed 0.15 mm per side. this dimension is determined at the plane where the bottom of the leads exit the plastic body. 5. this dimension does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25 mm per side. this dimension is determined at the plane where the bottom of the leads exit the plastic body. 6. this dimension does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed 0.4 mm per side. dambar cannot be located on the lower radius or the foot. minimum space between protrusion and adjacent lead shall not less than 0.07 mm. 7. exact shape of each corner is optional. 8. these dimensions apply to the flat section of the lead between 0.10 mm and 0.3 mm from the lead tip. 9. the package top may be smaller than the package bottom. this dimension is determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and inter-lead flash, but including any mismatch between the top and bottom of the plastic body. c l 10.9 7.4 1 16 17 32 0.10 a 2.35 seating plane 0.9 section b-b 0.65 r0.08 min b a pin 1 id (0.29) 0.38 0.25 (0.203) plating base metal section a-a rotated 90 clockwise 8 0.19 0.22 9 5 0.13 m ca m b 6 a c 7.6 11.1 9 4 10.3 5.15 a 32x 30x 2.65 0.3 a 2x 16 tips b c b 0.29 0.13 0.5 0 8 0 0.25 gauge plane min
analog integrated circuit device data freescale semiconductor 15 33395 revision history revision history revision date description of changes 3.0 7/2005 ? implemented revision history page ? converted to freescale format ? added pin definitions 4.0 2/2007 ? updated freescale data sheet form and style ? added mcz33395ew/r2 to the ordering information block ? removed peak package reflow temperature duri ng reflow (solder reflow) parameter and added notes (2) and (3) to maximum ratings on page 5
mc33395 rev 4.0 2/2007 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2007. all rights reserved. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http:// www.freescale.com/epp . rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http:// www.freescale.com/epp .

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